Hybrid Bonding Interconnect for Advanced Heterogeneously Integrated Processors

TLDR

Die stacking boosts computing performance, but conventional solder interconnects limit scaling; hybrid bonding overcomes these constraints, enabling orders‑of‑magnitude higher die‑to‑die connection density. The paper provides an overview of hybrid bonding technology and its capabilities for high‑performance computing applications. The authors describe the hybrid bonding process, its advantages over solder, and detail the design, manufacturing, and assembly steps of test chips along with fabrication results. Hybrid bonding improves signal integrity and reduces interconnect parasitics, cutting power consumption by over fivefold.

Abstract

Die stacking enables significant performance leaps in computing capability and memory/processor integration. Conventional die stacking uses solder interconnects which suffer from several scaling limitations. A new die to die interconnect technology, hybrid bonding, removes many of these limitations and allows several order of magnitude improvements in die-to-die connection density. In this paper, we provide an overview of hybrid bonding technology and its capabilities in the context of high-performance computing applications. The basic process & benefits of hybrid bonding vs. conventional solder interconnect are discussed. The signal integrity and power reduction benefits of hybrid bonding for several types of die-to-die interconnects are shown. We demonstrate that hybrid bonding can decrease the interconnect parasitics & correspondingly reduce the interconnect power by more than 5X. The design, manufacturing & assembly steps of our test chips and some of the fabrication results are also discussed.