A Half-micron Super Self-aligned BiCMOS Technology for High Speed Applications

Abstract

We report the process design, device characteristics and circuit performance of a new ultm high speed. high density, half-micron super self-aligned BiCMOS technology. Tht: minimum CMOS gate delay was measured to be 38 psec on 0.5 pm gate and 50 psec on 0.6 pm grte ring oscillators at 5 voll. Bipolar gate delay was measured to be 31 pscc on a 0.6pm emitter ECL ring oscillator. A single phase decision circuit operating error free at 8 Gblsec and a static frequency divider operating above 10 Gb/sec were demonstrated in our BiCMOS technology.