Deep Understanding of Negative Gate Voltage Restriction for SiC mosfet Under Wide Temperature Range

Abstract

In this letter, the origin and related physical insights of gate reliability issues under various <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> and high temperatures (up to 300 °C) are revealed in-depth, through splitting MOS gate structure of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) into N-type JFET and P-type channel region under identical manufacturing processes and thermal budgets of SiC MOSFETs. From 25 to 300 °C, the safety limit of positive <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> of SiC MOSFETs is mainly dependent on the gate oxide on the JFET surface, whereas that of negative <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> is dependent on the gate oxide on the channel surface. The gate oxide on the channel surface is weaker than that on the JFET surface in terms of Fowler–Nordheim (F-N) tunneling, resulting in asymmetric safety <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> of current SiC MOSFET. Moreover, when temperature ranges from 25 to 150 °C, the degradation of gate oxide under −15 V < <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> < 25 V is caused by the hole or electron direct tunneling mechanism. However, when the temperature reaches 300 °C, the degradation of gate oxide under −5 V < <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> < 10 V is caused by the hole or electron hopping conduction mechanism. Furthermore, the reliability of gate oxide is evaluated by the time-dependent dielectric breakdown measurement. The charge-to-breakdown ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</sub> ) of gate oxide is severely degraded at 300 °C mainly due to the barrier height ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${\it{ \Phi}}_{\rm B}$</tex-math></inline-formula> ) degradation. These efforts can provide accurate weakness points of gate oxide under higher <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> bias (particular for negative bias) and higher temperature (300 °C) for SiC MOSFETs, further helping use and design rugged converters with the fast-speed operation of SiC MOSFETs.