Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators

Abstract

This article comprehensively investigates analog-to-digital converter (ADC) design for compute-in-memory array. The authors show that 6-bit ADC precision is sufficient to guarantee no loss of accuracy for large arrays, while achieving the best tradeoff between hardware performance and area overhead, compared to prior state-of-the-art designs.