Neuro-Inspired Computing With Emerging Nonvolatile Memorys

TLDR

Neuro‑inspired computing with emerging nonvolatile memory devices is advancing, with key technologies such as phase‑change, resistive, ferroelectric, and floating‑gate memories being explored to address challenges and unlock future prospects. The review aims to outline the need for neuro‑inspired architectures beyond von‑Neumann, survey hardware design strategies—including digital/analog, spiking/non‑spiking, online/offline training—and present crossbar array and codesign approaches while projecting algorithm customization for efficient hardware. The authors detail synaptic device requirements—multilevel states, nonlinear weight updates, low variation—and review material prototypes, then describe crossbar array architectures for efficient weighted sums and weight updates, and outline peripheral neuron circuit design and device‑circuit‑algorithm codesign to assess nonideal device impacts on learning accuracy.

Abstract

This comprehensive review summarizes state of the art, challenges, and prospects of the neuro-inspired computing with emerging nonvolatile memory devices. First, we discuss the demand for developing neuro-inspired architecture beyond today's von-Neumann architecture. Second, we summarize the various approaches to designing the neuromorphic hardware (digital versus analog, spiking versus nonspiking, online training versus offline training) and discuss why emerging nonvolatile memory is attractive for implementing the synapses in the neural network. Then, we discuss the desired device characteristics of the synaptic devices (e.g., multilevel states, weight update nonlinearity/asymmetry, variation/noise), and survey a few representative material systems and device prototypes reported in the literature that show the analog conductance tuning. These candidates include phase change memory, resistive memory, ferroelectric memory, floating-gate transistors, etc. Next, we introduce the crossbar array architecture to accelerate the weighted sum and weight update operations that are commonly used in the neuro-inspired machine learning algorithms, and review the recent progresses of array-level experimental demonstrations for pattern recognition tasks. In addition, we discuss the peripheral neuron circuit design issues and present a device-circuit-algorithm codesign methodology to evaluate the impact of nonideal device effects on the system-level performance (e.g., learning accuracy). Finally, we give an outlook on the customization of the learning algorithms for efficient hardware implementation.