FeFET Memory Featuring Large Memory Window and Robust Endurance of Long-Pulse Cycling by Interface Engineering using High-k AlON

Abstract

Without destabilizing the ferroelectric (FE) phase, high-k AlON with [N] of ~ 13 % was proposed as the interfacial layer (IL) between FE HfZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> (HZO) and Si substrate for FeFET memory to enhance the memory window (MW) while improving reliability compared to SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> IL. The AlON-based memory shows promising performance in terms of a large MW of 3.1 V by ±4 V operation, long retention up to 10 years, and robust endurance up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> cycles with a long pulse width of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> s, outstanding other FeFET memory devices. It is ascribed to the high k value and larger ΔE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</sub> that respectively allow a lower voltage drop across the IL and suppress hole trapping. [N] in the IL also enhances the thermal stability that Inhibits sub-IL formation by restraining the reaction of residual OH groups with Si substrate. Besides, the AlON and FE-HZO can be integrated in a single ALD step to simplify the process. From device performance and process viewpoints, AlON paves a promising avenue to enable more reliable and feasible FeFET memory.