Enabling Multiple-Vt Device Scaling for CMOS Technology beyond 7nm Node

Abstract

For the first time, multiple-Vt (multi-Vt) device options with Vt range > 250 mV are achieved in standard cells at dimensions beyond 7nm technology node. To overcome the common scaling challenges of potential device options such as FinFET and gate all-around (GAA) nanosheet transistor — gate length and cell height scaling, key enablers are identified, including novel, thin, and conformal work function metal (WFM) with enhanced patterning efficiency, high-k (HK) engineering, and precise WFM patterning boundary control. This work enables design flexibility for advanced CMOS technology beyond 7nm node with critical differentiators.