4.5kV SiC Charge-Balanced MOSFETs with Ultra-Low On-Resistance

Abstract

We report successful design and fabrication of 4.5kV SiC charge-balanced MOSFET with R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</inf> of 10 mΩ.cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at 25 °C (20% below SiC unipolar limit). This device implements a novel scalable drift layer architecture for a high voltage switch as an alternative solution to super-junction devices. We have characterized the CB MOSFETs from room temperature up to 175 °C and show successful double pulse switching at 2.8kV and J <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</inf> =50 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Total switching loss is 110mJ/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at 25 °C and drops to 95mJ/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at 125 °C.