2020 · 89 citations · 38 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysReconfigurable ComputingAccelerator ArchitectureField-programmable Gate Array ArchitectureFpga ArchitectureMemory HierarchyMemory Hierarchy DesignMemory Subsystem DesignApplication StateApplication State ManagementBandwidth Bottleneck AnalysisHigh Bandwidth MemoryMemory BandwidthMemory Bandwidth OptimizationMemory Bottleneck Analysis
FPGAs are increasingly equipped with High Bandwidth Memory to alleviate memory bandwidth bottlenecks, yet its performance characteristics on FPGAs remain poorly defined. This work introduces Shuhai, an open‑source FPGA benchmarking tool designed to bridge the gap between nominal HBM specifications and real‑world performance on a Xilinx Alveo U280. Shuhai employs custom FPGA logic to conduct deterministic, noise‑free measurements of HBM, enabling detailed profiling that can be extended to other FPGA boards and memory generations such as HBM3 and DDR3. Benchmarking on the Alveo U280 shows HBM can deliver up to 425 GB/s, and that performance varies significantly with usage patterns, underscoring the need to understand HBM behavior for optimal design.
FPGAs are starting to be enhanced with High Bandwidth Memory (HBM) as a way to reduce the memory bandwidth bottleneck encountered in some applications and to give the FPGA more capacity to deal with application state. However, the performance characteristics of HBM are still not well specified, especially in the context of FPGAs. In this paper, we bridge the gap between nominal specifications and actual performance by benchmarking HBM on a state-of-the-art FPGA, i.e., a Xilinx Alveo U280 featuring a two-stack HBM subsystem. To this end, we propose Shuhai, a benchmarking tool that allows us to demystify all the underlying details of HBM on an FPGA. FPGA-based benchmarking should also provide a more accurate picture of HBM than doing so on CPUs/GPUs, since CPUs/GPUs are noisier systems due to their complex control logic and cache hierarchy. Since the memory itself is complex, leveraging custom hardware logic to benchmark inside an FPGA provides more details as well as accurate and deterministic measurements. We observe that 1) HBM is able to provide up to 425 GB/s memory bandwidth, and 2) how HBM is used has a significant impact on performance, which in turn demonstrates the importance of unveiling the performance characteristics of HBM so as to select the best approach. Shuhai can be easily generalized to other FPGA boards or other generations of memory, e.g., HBM3, and DDR3. We will make Shuhai open-source, benefiting the community.
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HBM (High Bandwidth Memory) DRAM Technology and Architecture
Hong-Shin Jun, Jin-Hee Cho, Kangseol Lee et al. · 2017 · 244 citations
Engineering, Computer Engineering, Electrical Engineering +17
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A quantitative analysis on microarchitectures of modern CPU-FPGA platforms
Young Choi, Jason Cong, Zhenman Fang et al. · 2016 · 118 citations · Full text