fpgaConvNet: A Framework for Mapping Convolutional Neural Networks on FPGAs

TLDR

Convolutional Neural Networks deliver state‑of‑the‑art accuracy but their computational demands grow rapidly. This paper introduces fpgaConvNet, a domain‑specific framework and automated methodology for mapping ConvNets onto FPGA platforms. The framework models ConvNet inference as a streaming application using the Synchronous Dataflow model and applies graph transformations to explore the performance‑resource trade‑off while respecting platform constraints. Compared with prior FPGA ConvNet designs, the fully automated method achieves up to 1.62× higher performance density and reaches 90.75% of the raw performance of hand‑tuned architectures.

Abstract

Convolutional Neural Networks (ConvNets) are a powerful Deep Learning model, providing state-of-the-art accuracy to many emerging classification problems. However, ConvNet classification is a computationally heavy task, suffering from rapid complexity scaling. This paper presents fpgaConvNet, a novel domain-specific modelling framework together with an automated design methodology for the mapping of ConvNets onto reconfigurable FPGA-based platforms. By interpreting ConvNet classification as a streaming application, the proposed framework employs the Synchronous Dataflow (SDF) model of computation as its basis and proposes a set of transformations on the SDF graph that explore the performance-resource design space, while taking into account platform-specific resource constraints. A comparison with existing ConvNet FPGA works shows that the proposed fully-automated methodology yields hardware designs that improve the performance density by up to 1.62× and reach up to 90.75% of the raw performance of architectures that are hand-tuned for particular ConvNets.