HBM (High Bandwidth Memory) DRAM Technology and Architecture

TLDR

HBM is an emerging DRAM standard that delivers over 256 GB/s bandwidth while lowering power consumption through a stacked architecture using TSV and die‑stacking technologies. The paper introduces the HBM architecture and compares its successive generations. It describes HBM packaging, reliability and thermal challenges, size limits, high‑throughput stacking solutions, and testability features for KGSD and 2.5D SiP.

Abstract

HBM (High Bandwidth Memory) is an emerging standard DRAM solution that can achieve breakthrough bandwidth of higher than 256GBps while reducing the power consumption as well. It has stacked DRAM architecture with core DRAM dies on top of a base logic die, based on the TSV and die stacking technologies. In this paper, the HBM architecture is introduced and a comparison of its generations is provided. Also, the packaging technology and challenges to address reliability, thermal dissipation capability, maximum allowable package sizes, and high throughput stacking solutions are described. Test technology and testability features are discussed for KGSD and 2.5D SiP.