A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feedforward Ring Oscillator-Based TDCs

Abstract

A power and area efficient two-step hybrid voltage-time ADC achieves a 4-GS/s conversion speed and 39.9-dB SNDR in 28-nm CMOS. Two pipelined time-based converters (TBCs) with a thermometer capacitive DAC (CDAC) in the ADC lead to a high-speed and low-power operation. The pipelined architecture splits the full ADC resolution, thus relaxing the TBC complexity. The TBC consists of a voltage-domain comparator, a current-source-based voltage-to-time converter (VTC), and a ring oscillator (RO)-based time-to-digital converter (TDC) with feedforward and 2× interpolation that achieves high conversion speed and good linearity simultaneously. The prototype ADC is fabricated in a standard 28-nm CMOS process with an active area of only 0.017mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured SNDR and SFDR are 39.9 and 47.8 dB with a Nyquist input at 4 GS/s. The FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</sub> and FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> are 39.3 fJ/conv-step and 152.2 dB, respectively.