Optimization of Performance and Reliability in 3D NAND Flash Memory

Abstract

3D NAND Flash with high storage capacity is in great demand for several technologies, which requires high performance and good reliability at the same time. Therefore, it is proposed to adjust the tunnel layer by changing the first SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (O1) layer thickness near poly Si channel in the tunnel layer based on SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> structure. The optimal thickness of O1 layer is found. Under the optimal condition, program speed increased by 19% compared with no O1 layer deposition, though erase speed is slightly decreased by about 7%, the initial threshold voltage shift is improved greatly. Experimental results demonstrate that there are complex mechanisms affected by the dielectric constant, band barrier and equivalent oxide thickness. The optimization of O1 layer is useful towards an understanding of program/erase speed and retention characteristics.