Bias-Induced Threshold Voltage Instability and Interface Trap Density Extraction of 4H-SiC MOSFETs

Abstract

In this paper, the results of electrical reliability measurements of commercially available 1200 V Silicon Carbide (SiC) MOSFETs are reported. The threshold voltage shift caused by interface states and the trapped charges near the SiC/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface is observed under positive and negative DC-bias-stress over 50 hours. Threshold voltage reduction with temperature is also reported for devices from different vendors. Negative shift of subthreshold characteristics under the negative bias stress and high drain bias at elevated temperature indicates that the threshold voltage of the devices should be increased by at least 1-2 V. Extracted interface state density using subthreshold I-V curves indicates very different SiC/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface for devices from different vendors.