A novel integration of STT-MRAM for on-chip hybrid memory by utilizing non-volatility modulation

Abstract

We demonstrate a novel way of integrating STT-MRAM for on-chip hybrid memory which exhibits either features of high-retention or high-speed implemented in separate zones in a single chip. For satisfying high-temperature retention requirement, tailored MTJs are shown to support > 10 year retention at 220°C. For high-speed operation, critical improvements have been made in terms of TMR, short fail probability, overdrive and write error rate. The new integration provides a manufacturable way of combining diverse memory components by modulating non-volatility of STT-MRAM without affecting within-chip distributions of critical properties.