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A Multilevel FeFET Memory Device based on Laminated HSO and HZO Ferroelectric Layers for High-Density Storage

134

Citations

3

References

2019

Year

Abstract

We report 1-3 bit/cell FeFET operation through optimized HSO and HZO ferroelectric laminate layers using alumina interlayers. Memory window up to 3.5V, switching speed of 300ns, 10 years retention, and 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> endurance are reported. The gate stack lamination merits are discussed with insight potential of FeFET as an MLC memory.

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