Philosophical Transactions of the Royal Society A Mathematical Physical and Engineering Sciences · 2020 · 501 citations · 22 references
EngineeringComputer ScienceInformation TechnologyComputer ArchitectureMicroelectronicsSemiconductor DevicesDevice ScalingPerformance OptimizationDevice Scaling EffectsFabricationMiniaturizationMoore's Law ScalingSiliconTechno-economic AnalysisTechnological OpportunitiesTechnology Scaling
Moore's Law is a techno-economic model that has enabled the information technology industry to double the performance and functionality of digital electronics roughly every 2 years within a fixed cost, power and area. Advances in silicon lithography have enabled this exponential miniaturization of electronics, but, as transistors reach atomic scale and fabrication costs continue to rise, the classical technological driver that has underpinned Moore's Law for 50 years is failing and is anticipated to flatten by 2025. This article provides an updated view of what a post-exascale system will look like and the challenges ahead, based on our most recent understanding of technology roadmaps. It also discusses the tapering of historical improvements, and how it affects options available to continue scaling of successors to the first exascale machine. Lastly, this article covers the many different opportunities and strategies available to continue computing performance improvements in the absence of historical technology drivers. This article is part of a discussion meeting issue 'Numerical algorithms for high-performance computational science'.
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Cramming More Components Onto Integrated Circuits
Gordon E. Moore · Proceedings of the IEEE · 1998 · 5.8K citations
In-Datacenter Performance Analysis of a Tensor Processing Unit
Norman P. Jouppi, Cliff Young, Nishant Patil et al. · 2017 · 4.4K citations
The Landscape of Parallel Computing Research: A View from Berkeley
Krste Asanović, Ras Bodik, Bryan Catanzaro et al. · 2006 · 2K citations
Engineering, Computer Science, High-performance Computing +17
In-Datacenter Performance Analysis of a Tensor Processing Unit
Norman P. Jouppi, Cliff Young, Nishant Patil et al. · ACM SIGARCH Computer Architecture News · 2017 · 1.3K citations · Full text