Rationale and challenges for optical interconnects to electronic chips

TLDR

Optical interconnects promise to address key interconnect challenges—such as clock distribution, synchronization, bandwidth, density, power, crosstalk, impedance, and scaling—without requiring new physical breakthroughs, though cost and technology development remain significant barriers. The paper reviews the arguments for adopting optical interconnects to silicon CMOS chips and discusses the associated optical, optoelectronic, and integration challenges. An appendix analyzes how line inductance and skin effect constrain the scaling of on‑chip global electrical interconnects.

Abstract

The various arguments for introducing optical interconnections to silicon CMOS chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed. Optics could solve many physical problems of interconnects, including precise clock distribution, system synchronization (allowing larger synchronous zones, both on-chip and between chips), bandwidth and density of long interconnections, and reduction of power dissipation. Optics may relieve a broad range of design problems, such as crosstalk, voltage isolation, wave reflection, impedence matching, and pin inductance. It may allow continued scaling of existing architectures and enable novel highly interconnected or high-bandwidth architectures. No physical breakthrough is required to implement dense optical interconnects to silicon chips, though substantial technological work remains. Cost is a significant barrier to practical introduction, though revolutionary approaches exist that might achieve economies of scale. An Appendix analyzes scaling of on-chop global electrical interconnects, including line inductance and the skin effect, both of which impose significant additional constraints on future interconnects.