2002 · 29 citations · 12 references
EngineeringComputer EngineeringComputer ScienceCompilersComputer ArchitectureInterconnection NetworksBuffer ManagementHigh-level SynthesisInterconnect ArchitectureInterconnect DesignMemory Hierarchy DesignMemory Hierarchy OptimizationBuffer InsertionBuffer OptimizationBuffer PlacementBuffer TreesHardware PipeliningLocality ConstraintsTemporal LocalityTemporal Locality Exploitation
We give an overview of a buffer tree synthesis package which pays particular attention to the following issues: routing and buffer blockages, minimization of interconnect and buffer costs, exploitation of temporal locality among the sinks and addressing sink polarity requirements. Experimental results demonstrate the effectiveness of the tool in comparison with previously proposed techniques.
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