Designing a Second Order Generalized Integrator Digital Phase Locked Loop based on a Frequency Response Approach

Abstract

This paper presents a Digital Phase-Locked Loop (PLL) based on the Second Order Generalized Integrator (SOGI). The PLL structure, as well as the SOGI, are carefully described. The integrators of the SOGI are explained in detail in order to emphasize the elimination of an algebraic loop found in continuous time domain PLLs. The main contributions of this paper are to present the design of PLL entirely in z-domain and to present an easy, fast and accurate way to implement a digital PLL based on the SOGI structure. The digital SOGI PLL is implemented in the digital signal processor TMS320F28335. Experimental and simulation results show the efficacy of the digital SOGI PLL to keep synchronized with grid voltage at frequencies 50 and 60 Hz.