Addressing DC Component in PLL and Notch Filter Algorithms

Abstract

This paper presents a method for addressing the dc component in the input signal of the phase-locked loop (PLL) and notch filter algorithms applied to filtering and synchronization applications. The dc component may be intrinsically present in the input signal or may be generated due to temporary system faults or due to the structure and limitations of the measurement/conversion processes. Such a component creates low-frequency oscillations in the loop that cannot be removed using filters because such filters will significantly degrade the dynamic response of the system. The proposed method is based on adding a new loop inside the PLL structure. It is structurally simple and, unlike an existing method discussed in this paper, does not compromise the high-frequency filtering level of the concerned algorithm. The method is formulated for three-phase and single-phase systems, its design aspects are discussed, and simulations/experimental results are presented.