IEEE Access · 2019 · 35 citations · 15 references
EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyIntegrated Circuit DesignMos CapacitorsPower OptimizationSubthreshold Circuit DesignCmos Analog Integrated CircuitsCmos ScalingLow-power Cmos DesignLow-power MultipliersMultiplication FactorMultiplier DesignPower ConsumptionSubthreshold Operation
This paper presents a CMOS floating and tunable capacitance multiplier with a very large multiplication factor. The proposed design uses CCII and OTAs designed using MOSFETs biased in subthreshold region to provide low power consumption and high multiplication factor. TANNER TSPICE simulation tool is used to confirm the functionality of the design in 0.18μm TSMC CMOS technology. The circuit is powered using ±0.75V DC supply voltage. Simulation results indicate that the maximum multiplication factor is 3600 and the maximum error is 8.6%.
15