2019 · 19 citations · 21 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysMachine LearningAccelerator ArchitectureDeep LearningField-programmable Gate Array ArchitectureFpga ArchitectureHardware AccelerationLow-power Fpga DesignAccuracyComputational EfficiencyDesign For FlexibilityEnergy-efficient Hardware AccelerationField-programmable Gate Arrays (Fpgas)Hardware ResourcesMultiply-accumulate UnitsPower-efficient Accelerator Design
To improve the throughput and energy efficiency of Deep Neural Networks (DNNs) on customized hardware, lightweight neural networks constrain the weights of DNNs to be a limited combination (denoted as k ϵ {1, 2}) of powers of 2. In such networks, the multiply-accumulate operation can be replaced with a single shift operation, or two shifts and an add operation. To provide even more design flexibility, the k for each convolutional filter can be optimally chosen instead of being fixed for every filter. In this paper, we formulate the selection of k to be differentiable, and describe model training for determining k-based weights on a per-filter basis. Over 46 FPGA-design experiments involving eight configurations and four data sets reveal that lightweight neural networks with a flexible k value (dubbed FLightNNs) fully utilize the hardware resources on Field Programmable Gate Arrays (FPGAs), our experimental results show that FLightNNs can achieve 2× speedup when compared to lightweight NNs with k = 2, with only 0.1% accuracy degradation. Compared to a 4-bit fixed-point quantization, FLightNNs achieve higher accuracy and up to 2× inference speedup, due to their lightweight shift operations. In addition, our experiments also demonstrate that FLightNNs can achieve higher computational energy efficiency for ASIC implementation.
21
MobileNetV2: Inverted Residuals and Linear Bottlenecks
Mark Sandler, Andrew Howard, Menglong Zhu et al. · 2018 · 25.4K citations
MobileNetV2: Inverted Residuals and Linear Bottlenecks
Mark Sandler, Andrew Howard, Menglong Zhu et al. · arXiv (Cornell University) · 2018 · 2.3K citations · Full text
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
Chen Zhang, Peng Li, Guangyu Sun et al. · 2015 · 2.1K citations