A 2.2-GHz 3.2-mW DTC-Free Sampling $\Delta\Sigma$ Fractional-$N$ PLL With −110-dBc/Hz In-Band Phase Noise and −246-dB FoM and −83-dBc Reference Spur

Abstract

This paper presents the first sampling ΔΣ fractional-N phase-locked loop (PLL) without a digital-to-time converter (DTC), whose design is challenging and requires complex calibration. A linear slope generator (LSG) is employed to generate a linear waveform, which has a large linear phase-to-voltage conversion range. Instead of modulating the reference signal by the DTC, phase dithering is performed at the feedback path through the combination of the LSG and a multi-modulus divider (MMDIV) with multi-phase generation. The reference signal then directly samples the linear LSG output waveform to output a sampled voltage corresponding linearly to the resulting phase error. All these enable the sampling phase detector to handle large phase dither step provided by a phase interpolator (PI), thus eliminating the need for the DTC and the associated calibration. This 2.2-GHz PLL achieves -246-dB FoM with an in-band phase noise of -110 dBc/Hz and -82-dBc reference spur while consuming only 3.2 mW in a 130-nm CMOS process.