19.5 Digital Leakage Compensation for a Low-Power and Low-Jitter 0.5-to-5GHz PLL in 10nm FinFET CMOS Technology

Abstract

As the push for low-power, low-jitter, and low-area phase-locked loop (PLL) design [1] continues in the 10nm node and beyond, the leakage from various sources could become an issue in the applications where the reference clock frequency is low and the static phase error is required to be close to zero at all process corners and temperatures. The impacts of leakage currents on analog PLLs are the increase of static phase error, higher jitter and reference spur. To mitigate the leakage sensitivity in analog PLL designs, digital PLLs have been designed [2-3], but they often exhibit higher power consumption and higher jitter due to quantization noise, and require high-performance voltage regulators or supply-noise cancellation techniques [4] due to their high sensitivity to power-supply noise. To compensate for the leakage current in analog PLLs, analog compensation circuits are proposed [5-6], but it is impossible to achieve zero or low phase error across PVT corners.