Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL

Abstract

A self-biased phase-locked loop (PLL) uses a sampled feedforward filter network and a multistage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of multiplication factor, output frequency, process, voltage, and temperature. The PLL achieves a multiplication range of 1-4096 with less than 1.7% output jitter. Fabricated in 0.13-μm CMOS, the area is 0.182mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the supply is 1.5 V.