Self-biased, high-bandwidth, low-jitter 1-to-4096 multiplier clock-generator PLL

Abstract

A self-biased PLL uses a sampled feed-forward filter network and a multi-stage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of multiplication factor, output frequency, and PVT. The PLL achieves a multiplication range of 1 to 4096 with < 3.8% period jitter at 1.5V supply. Fabricated in 0.13/spl mu/m CMOS, the area is 0.182mm/sup 2/ and the supply is 1.5V.