STT-MRAM devices with low damping and moment optimized for LLC applications at Ox nodes

Abstract

Last-Level-Cache applications at 0X technology nodes require devices switching reliably in less than 10ns at currents smaller than 50uA, while preserving data retention up to 85°C. In this paper, we show that both low Gilbert damping and low magnetic moment are the primary factors for efficient writing at nanosecond time scales. We report comprehensive device-level measurements of damping using both conventional free layer designs and an optimized free layer that combines low damping and low moment and meets LLC requirements.