IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2018 · 17 citations · 10 references
EngineeringComputer EngineeringElectrical EngineeringDigital CommunicationMicroelectronicsSemiconductor DevicesCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsIntegrated Circuit DesignLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignCmos Logic CircuitsFeedback DelayFlip-flop DesignHigh-speed Cmos DesignHigh-speed OperationLatch DesignLow-power Latch DesignRf Cmos Design
In this brief, a 0.9-V 12-Gb/s quarter-rate two finite impulse response tap direct decision feedback equalizer (DFE) is presented. For a high-speed incorporated operation of both DFE summing and slicing, a common-mode-controlled charge-based latch (CMCCBL) is proposed. In a CMCCBL-based DFE, the common mode of the first tap feedback signal is changed to adjust the first tap feedback weight. Therefore, CMCCBL does not need the conventional first tap weighting transistors which increase the DFE feedback delay. The DFE core compensates for the FR4 printed circuit board channel loss of −22 dB at 6 GHz and consumes 4.16 mW achieving 0.347 pJ/bit for PRBS7 input. The active area of DFE is 0.0036 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a 65-nm CMOS process.
10
Seuk Son, Han-Seok Kim, Myeong-Jae Park et al. · IEEE Journal of Solid-State Circuits · 2013 · 32 citations
Engineering, Computer Engineering, Electrical Engineering +16