IEEE Transactions on Circuits and Systems I Regular Papers · 2018 · 11 citations · 18 references
EngineeringCommunicationElectrical EngineeringAnalog ElectronicsDigital CommunicationSystem-on-chip DesignChannel CodingCmos Circuit DesignCoding TheoryMixed-signal Integrated Circuit DesignPulse-width ModulationCoding SchemesEncoder DesignEnergy-efficient CommunicationEqualizationHigh-speed Cmos DesignPulse Width Modulation TechniquesTransceiver ArchitecturesTransceiver Design
This paper presents two new line-coding schemes, integrated pulse width modulation (iPWM) and consecutive digit chopping (CDC) for equalizing lossy wireline channels with the aim of achieving energy efficient wireline communication. The proposed technology friendly encoding schemes are able to overcome the fundamental limitations imposed by Manchester or pulse-width modulation encoding on high-speed wireline transceivers. A highly digital encoder architecture is leveraged to implement the proposed iPWM and CDC encoding. Energy-efficient operation of the proposed encoding is demonstrated on a high-speed wireline transceiver that can operate from 10 to 18 Gb/s. Fabricated in a 65-nm CMOS process, the transceiver operates with supply voltages of 0.9 V, 1 V, and 1.1 V. With the help of the proposed iPWM encoding, the transceiver can equalize over 27-dB of channel loss while operating at 16 Gb/s with an efficiency of 4.37 pJ/bit. The design occupies an active die area of 0.21 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .
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A 27-mW 3.6-Gb/s I/O Transceiver
K.-L.J. Wong, Hamid Hatamkhani, Mozhgan Mansuri et al. · IEEE Journal of Solid-State Circuits · 2004 · 121 citations
Engineering, Computer Engineering, Electrical Engineering +17
A 10Gb/s CMOS adaptive equalizer for backplane applications
Srikanth Gondi, Jri Lee, Daisuke Takeuchi et al. · 2005 · 72 citations
Engineering, Computer Engineering, Electrical Engineering +16