Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver

Abstract

To achieve high bit rates link designers are using more sophisticated communication techniques, often turning to 4PAM transmission or decision-feedback equalization (DFE). Interestingly, with only minor modification the same hardware needed to implement a 4PAM system can be used to implement a loop-unrolled single-tap DFE receiver. To get the maximum performance from either technique, the link has to be tuned to match the specific channel it is driving. Adaptive equalization using data based update filtering allows continuous updates while minimizing the required sampler front-end hardware and significantly reduces the cost of implementation in multi-level signaling schemes. A transceiver chip was designed and fabricated in 0.13 /spl mu/m CMOS process to investigate dual-mode operation and the modifications of the standard adaptive algorithms necessary to operate in high-speed link environments.