Multi-Chip Patch in Low Stress Polymer Foils based on an Adaptive Layout for Flexible Sensor Systems

Abstract

Microelectronic developments in the context of More-than-Moore are heading towards smart systems which are intelligent, compact, flexible, and cost effective for applications in medical and consumer electronics or the internet of things (IoT). Flexible Hybrid System-in-Foil (HySiF) satisfy these requirements by embedding ultra-thin chips in a polymer foil to combine low-cost, large and flexible organic with high performance silicon chips. On the way to implement more and more components in foil, the Chip-Film Patch (CFP) technology is developed by exploiting the adaptive layout technique. CFP is based on CMOS compatible tools and processes, thus exploiting the advantages and establishments of scaled CMOS technologies. In this paper, a HySiF based on CFP technology is demonstrated through embedding and interconnection of two commercial CMOS chips. Any misalignment of the embedded chips is compensated by a smart lithography step using a laser direct writing tool that allows pattern recognition and layout adjustments by an adaptive layout technique. This leads to higher I/O counts and smaller pad sizes. All processing steps are discussed and, in the end, the process is verified by electrical verification of the micro-controller and NFC chips.