A 12.1 fJ/Conv.-Step 12b 140 MS/s 28-nm CMOS Pipelined SAR ADC Based on Energy-Efficient Switching and Shared Ring Amplifier

Abstract

This brief presents an ultra-low-power two-channel 12b 140 MS/s 28-nm CMOS analog-to-digital converter (ADC) for use in next-generation mobile communications systems. The proposed ADC employs a two-stage pipelined successive-approximation register (SAR) ADC architecture, where the SAR ADC at each stage determines 5b and 8b, respectively. In the first-stage 5b SAR ADC, the switching power consumption is significantly reduced due to the switching operation by only a separate digital-to-analog converter (DAC) with a small unit capacitance, which generates the comparator decision threshold. When this setup is applied to an actual system, the reference voltage driver of the system is less burdened. Furthermore, the SAR ADC employs a custom-encapsulated capacitor to improve the limited linearity of a DAC caused by parasitic capacitance. A residue amplifier employs an ultra-low power ring amplifier structure. The amplifier is shared by each channel to reduce not only the power consumption and die area but also channel mismatches. The prototype ADC in a 28-nm CMOS process demonstrates a measured differential non-linearity and integral non-linearity within 1.50 LSB and 2.85 LSB at 12b, respectively, with a maximum signal-to-noise-and-distortion ratio and a spurious-free dynamic range of 58.0 dB and 73.7 dB at 140 MS/s, respectively. The ADC occupies an active die area of 0.202 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 1.1 mW at a 0.8-V supply voltage, corresponding to a figure of merit of 12.1 fJ/conversion-step.