IEEE Journal of Solid-State Circuits · 2018 · 78 citations · 22 references
EngineeringDigital DesignElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignMixed-signal IntegrationAdaptive SamplingCmos OscillatorsLow-dropout Regulator DesignLow-dropout RegulatorsLow-power Cmos DesignLow-power Flip-flop DesignVoltage-controlled Oscillator DesignVoltage-controlled Oscillators
This paper proposes a fully integrated digital low-dropout (DLDO) regulator using a beat-frequency (BF) quantizer implemented in a 65-nm low power (LP) CMOS technology. A time-based approach, replacing the conventional voltage quantizer by a pair of voltage-controlled oscillator and a time quantizer, makes the design highly digital. A D-flip-flop is utilized as a BF generator, which is used as the sampling clock for the DLDO. The variable sampling frequency in the BF DLDO can achieve fast response, LP consumption, and excellent stability at the same time. In addition to that, the DLDO has a built-in active voltage positioning (AVP) for lower peak-to-peak voltage deviation during load step. The load capacitor is only 40 pF, and the total core area of the DLDO is 0.0374 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . A 50-mA step in load current produces a voltage droop of 108 mV, which is recovered in 1.24 μs. It can operate for a wide input voltage from 0.6 to 1.2 V while generating a 0.4-1.1-V output for a maximum load current of 100 mA. The peak current efficiency is 99.5% and the figure of merit (FOM) is 1.38 ps.
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