Effective Drive Current in Scaled FinFET and NSFET CMOS Inverters

Abstract

This work investigates the impact of CMOS scaling on the DC effective drive current, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{eff}$</tex> [1], <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{eff}=1/2\times(I_{high}+I_{low})=1/2\times [d_{s}(V_{gs}=0.5V_{dd},V_{ds}=V_{dd})+(V_{gs}=V_{dd},V_{ds}=V_{dd}/2)$</tex> ] of aggressively scaled MOSFETs down to 7nm node technology. FinFET and Nanosheet (NSFET) architectures [2], [3] behave similarly, and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$l_{eff)}$</tex> continues to predict the intrinsic delay for aggressively scaled MOSFETs for both device architectures, even for supply-voltages <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(V_{dd})$</tex> as low as ~0.2V, where these devices operate in the subthreshold regime. The ratio of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$l_{eff}/I_{on}, I_{on}=I_{ds}(V_{ds}=V_{gs}=V_{dd})$</tex> , as a function of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{dd}$</tex> , and threshold voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(V_{th})$</tex> ) show that this ratio can be significantly modulated about a typical value of ~0.5, in a manner that can be easily related to classical MOSFET behavior.