Novel CMOS multi-bit counter for speed-power optimization in multiplier design

A Suggestion for a Fast Multiplier

Christopher S. Wallace · IEEE Transactions on Electronic Computers · 1964 · 1.8K citations

Engineering, Computer Architecture, Supercomputer Architecture +19

A new design technique for column compression multipliers

Zhongde Wang, G.A. Jullien, William C. Miller · IEEE Transactions on Computers · 1995 · 129 citations

Column Compression, Lossy Compression, Column Compression Multipliers +14

High-speed multiplier design using multi-input counter and compressor circuits

M. Mehta, Vivek Parmar, Earl E. Swartzlander · 2002 · 89 citations

Electrical Engineering, Fast Multiplier, Engineering +11

Energy efficient implementation of parallel CMOS multipliers with improved compressors

Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija · 2010 · 74 citations

Engineering, Vlsi Design, Energy Efficiency +16

Design of an algorithmic Wallace multiplier using high speed counters

Shahzad Asif, Yinan Kong · 2015 · 59 citations

Engineering, Vlsi Design, Hardware Acceleration +12