IEICE Electronics Express · 2018 · 12 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsInstrumentationLow-power DesignAnalog Integrated CircuitsDigital Integrated CircuitsDigital Signal ProcessingLow-noise Circuit DesignMixed-signal Integrated Circuit DesignMixed-signal IntegrationAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital ConvertersComparator DesignComparatorsLinearityNonlinearitySignal-to-noise Ratio
In this paper, a 12-bit pipeline Analog-to-Digital (ADC) in 0.13 µm CMOS process with SHA-less structure is presented. Two kinds of high-speed comparators are proposed to reduce settling time of residue amplifier. Meanwhile, the foreground calibration algorithm can correct the mismatch of capacitors and alleviate the effect of finite gain of residue amplifier for better linearity. A single-to-differential reference voltage buffer which can be easily controlled by the reference voltage outside is also designed in this ADC. Measurement results show that the ADC achieves an spurious-free dynamic range (SFDR) of 83.6 dBc, a signal-to-noise ratio (SNR) of 67.16 dB and a signal-to-noise and distortion ratio (SNDR) of 66.9 dB with 9.95 MHz input signal at 120 MS/s. The integral nonlinearity (INL) and differential nonlinearity (DNL) are within ±0.8 LSB and ±0.25 LSB, respectively.
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Clocked comparator for high-speed applications in 65nm technology
Mohamed Abbas, Yasuo Furukawa, Satoshi Komatsu et al. · 2010 · 82 citations
Engineering, Computer Engineering, Electrical Engineering +17