2010 · 82 citations · 11 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsSemiconductor DevicesClock ManagementCmos Circuit DesignDigital Integrated Circuit DesignHigh-frequency Semiconductor DevicesMixed-signal Integrated Circuit DesignMixed-signal IntegrationClocking ArchitectureCmos ScalingComparator DesignComparatorsDigitizationHigh-speed Circuit DesignHigh-speed Cmos DesignMaximum Speed
This paper presents a design for an on-chip high-speed clocked-comparator for high frequency signal digitization. The comparator consists of two stages, amplification and regenerative, comprising a total of 10 MOS transistors. The design is implemented in 65nm CMOS technology. Also, the paper presents a new cost effective technique for measuring the maximum speed of the clocked comparator. The measurement and simulation results show that the proposed design has an average of 31% higher speed and ∼17% less active area than the conventional design.
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A low-noise self-calibrating dynamic comparator for high-speed ADCs
Masaya Miyahara, Yusuke Asada, Daehwa Paik et al. · 2008 · 414 citations
Engineering, Computer Engineering, Electrical Engineering +17