An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique

Abstract

Herein is presented an external capacitorless low-dropout regulator (LDO) that provides high-power-supply rejection (PSR) at all low-to-high frequencies. The LDO is designed to have the dominant pole at the gate of the pass transistor to secure stability without the use of an external capacitor, even when the load current increases significantly. Using the proposed adaptive supply-ripple cancellation (ASRC) technique, in which the ripples copied from the supply are injected adaptively to the body gate, the PSR hump that appears in conventional gate-poledominant LDOs can be suppressed significantly. Since the ASRC circuit continues to adjust the magnitude of the injecting ripples to an optimal value, the LDO presented here can maintain high PSRs, irrespective of the magnitude of the load current IL, or the dropout voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DO</sub> . The proposed LDO was fabricated in a 65-nm CMOS process, and it had an input voltage of 1.2 V. With a 240-pF load capacitor, the measured PSRs were less than -36 dB at all frequencies from 10 kHz to 1 GHz, despite changes of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DO</sub> as well as process, voltage, temperature (PVT) variations.