Full On-Chip CMOS Low-Dropout Voltage Regulator

TLDR

The authors propose a capacitorless low‑dropout regulator to replace bulky external‑capacitor LDOs for system‑on‑chip integration. They remove the large external capacitor, implement a compensation scheme that ensures fast transient response and full AC stability from 0 to 50 mA load with up to 100 pF output capacitance, and fabricate a 2.8‑V LDO in 0.35‑µm CMOS consuming only 65 µA of ground current and 200 mV dropout. Experimental results confirm that the capacitorless design eliminates the load‑transient and AC‑stability problems seen in prior architectures.

Abstract

This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (AC) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-mum CMOS technology, consuming only 65 muA of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures.