IEEE Electron Device Letters · 2018 · 21 citations · 12 references
EngineeringComputer EngineeringElectrical EngineeringMemoryMicroelectronicsSemiconductor DevicesMemory DevicesMemory ModelingTiming Analysis3D Nand ArchitectureFlash MemoryFlash Memory DevicesMemory Circuit DesignNand Flash MemoryNon-volatile Memory DesignThree-dimensional MemoryTiming
A new program scheme using an “erase-like” waveform for precharge operation is proposed for program disturbance optimization in 3-D vertical channel flash memories. With the proposed scheme, the effect of precharge operation, which is followed by program operation, on the initial unselected channel is enhanced by charging additional holes from p-type well. Consequently, boosting efficiency and boosting potential of unselected string are promoted, leading to a significant suppressed program disturbance, and the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pass</sub> window can be enlarged notably as well. Meanwhile, the timing requirement of the proposed scheme is evaluated. The advantage of the erase assisted precharge scheme has been demonstrated by TCAD simulation and measurement in mini-array test-key device.
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New scaling limitation of the floating gate cell in NAND Flash Memory
Yong Seok Kim, Dong Jun Lee, Chi Kyoung Lee et al. · 2010 · 38 citations