Short-Circuit Ruggedness and Failure Mechanisms of Si/SiC Hybrid Switch

Abstract

The hybrid switch (HyS) of a higher-current main Si IGBT and a parallel lower-current auxiliary Silicon Carbide (SiC) mosfet offer an improved cost/performance tradeoff for practical power electronic designs. The purpose of this paper is to investigate the short-circuit (SC) ruggedness, failure mechanisms, and techniques for improvement of the Silicon/SiC HyS. The influence of major limiting factors, including dc bus voltage, gate drive voltage, gate control pattern, case temperature, and SiC mosfet sizing are experimentally studied. Two SC failure mechanisms, the thermal runaway and gate interlayer dielectric breakdown of the SiC mosfet are identified using microscopic failure analysis techniques. An optimum gate control selection is proposed to improve the HyS's SC withstanding time with minimum increase in its power loss.