A 12-bit, 2.5-bit/cycle, 1 MS/s two-stage cyclic ADC, for high-speed CMOS Image sensors

Abstract

A 12-bit, 1 MS/s, two-stage cyclic ADC, with novel 2.5-bit/cycle architecture is proposed in this paper. A 1.5-bit algorithm is used in a 2.5-bit framework, which reduces the required number of accurate comparators and power consumption by 42%. Further, the ADC shows 46% improvement in the conversion rate as compared to the state-of-the-art two-stage cyclic ADC. The proposed ADC is designed and fabricated in a standard 180 nm CMOS technology. The obtained values of DNL and INL are +0.5/-0.5 LSB and +0.8/-0.9 LSB respectively. The ADC consumes 0.8 mW of power and occupies an area of 0.045 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a FoM of 0.19 pJ/conversion-step. The proposed ADC when designed in a column pitch of 5.6 μm, will result in a frame-rate of 1000 frames/sec for a 1 Mpixel array.