Design and implementation of multibit LFSR on FPGA to generate pseudorandom sequence number

Abstract

Pseudorandom number generators (PRNGs) are important role in cryptography application. Hardware based random number generators become faster. Field Programming Gate Arrays (FPGA) is one of the most valuable devices in hardware industry. This paper presents multibit linear feedback shift register (LFSR) based PRNGs circuit designed with hardware description languages (HDL). In multibit LFSR system, multiple bits are shift in every clock cycle where a single bit is shift in a conventional LFSR method. This technique is very much applicable in cryptography area. The proposed various bit length multibit LFSR architectures are synthesized using Xilinx ISE 14.7 and Spartan 6 FPGA to target device XC6SLX45. The result analysis indicates that 32-bit length multibit LFSR architecture is better performance than other architectures.