Scaling challenges of FinFET architecture below 40nm contacted gate pitch

Abstract

In addition to electrostatics challenges, FinFETs scaled below CPP of 40nm will require ρC of -8×1010Ω-cm2 if performance gains are to be extended. Attainment of ρC at fully ohmic limit, and/or innovative contact structures, will be required if FinFETs are to extend performance gains below CPP of 30nm, or else a transition to a new device architecture will be required.