2017 · 23 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsDevice ScalingIntegrated Circuit DesignLow-power Digital Circuit DesignPower ManagementPower OptimizationScale-up DesignCmos ScalingComplementary Metal-oxide-semiconductor ScalingDevice Scaling EffectsFin Field-effect Transistor ScalingGate Oxide ScalingScaling Effects In CmosStress EffectsTechnology Scaling
The industry's first 10nm low power high performance mobile SoC has been successfully ramped in production. Thanks to a thorough design-technology co-development, 10nm SoC is 16% faster, 37% smaller, and 30% lower power than its 14nm predecessor. The latest SoC features a gigabit class modem and is set to advance AR/VR, AI, machine learning, and computing. 10nm FinFet technology scaling challenges such as sharply increased wiring resistance and variation and strong layout stress effects are discussed to illustrate design and technology co-development from technology definition to product ramp stage is imperative to realize scaling entitlements.