A 10-b 2b/cycle 300MS/s SAR ADC with a single differential DAC in 40nm CMOS

Abstract

This paper presents a 2b/cycle hybrid successive-approximation-register (SAR) analog-to-digital-converter (ADC) architecture with only 1 differential capacitor-DAC (CDAC). Unlike prior multi-bit/cycle SAR works that make use of only the DAC differential mode (DM) voltage, the proposed architecture exploits both the DM and the common mode (CM). By using two degrees of freedom, the proposed ADC can generate 3 comparison levels needed for 2b/cycle without requiring extra DAC arrays. Eliminating extra DAC arrays reduces hardware cost, area, and power. The proposed SAR ADC takes advantage of 1b/cycle conversion mode and sufficient redundancy to address problems of multi-bit/cycle conversions, such as unmatched comparator offsets, kickback noise, and comparator input CM voltage variation. Reconfiguration to 1b/cycle is easily done by disabling the unneeded comparators for 1b/cycle conversion. A 10b prototype ADC is fabricated in 40nm LP CMOS process. It achieves peak 8.5b ENOB at sampling frequency of 300MS/s and consumes 2.1mW, leading to a FoM of 19.3fJ/conv-step.