A low-power 8-PAM serial transceiver in 0.5-μm digital CMOS

D.J. Foley, Michael P. Flynn

IEEE Journal of Solid-State Circuits · 2002 · 62 citations · 6 references

Concepts

Abstract

An 8-PAM CMOS transceiver is described in this paper. Pre-emphasis is implemented without an increase in DAC resolution or digital computation. The receiver oversamples with three fully differential 3-bit ADCs. The prototype transmits at up to 1.3 Gb/s and has a measured bit error rate of less than 1 in 10/sup 13/ for an 810-Mb/s pseudorandom bit sequence transmission. The device, packaged in a 68-pin ceramic leadless chip carrier, is implemented in 0.5-/spl mu/m digital CMOS, occupies 2 mm/sup 2/, and dissipates 400 mW from a 3.3-V supply.

References

6