R. Farjad-Rad - Concepedia

Author

R. Farjad-Rad

Stanford University

Also Known As

R. Farjad-Rad, Ramin Farjad-Rad, Ramin Farjadrad

Publications

1.2K

Citations

H-Index

Concepts

All Affiliations

Stanford University Stanford SystemX Alliance Integrated Systems Solutions (United States)Rambus (United States)

About

R. Farjad-Rad is an author at Stanford University specializing in computer engineering, engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	12	13	1.1K
2	Computer Engineering	12	13	1.1K
3	Electrical Engineering	5	5	386
4	Biomedical Engineering	1	1	45
5	Systems Engineering	1	1	135

R. Farjad-Rad

Publications

1.1K

Citations

H-Index

Page 1

	Year	Citations
A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips R. Farjad-Rad, William J. Dally, Hiok-Tiaq Ng, IEEE Journal of Solid-State Circuits Electrical EngineeringEngineeringVlsi DesignClock MultiplierClock Recovery	2002	210
A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver R. Farjad-Rad, C.-K.K. Yang, Mark Horowitz IEEE Journal of Solid-State Circuits Frequency Acquisition AidEngineeringClock RecoveryReceive EqualizationMixed-signal Integrated Circuit	2000	164
Jitter transfer characteristics of delay-locked loops - theories and design techniques M.-J.E. Lee, William J. Dally, Thomas H. Greer, IEEE Journal of Solid-State Circuits Jitter PeakingTime Delay SystemJitter Transfer CharacteristicsDesign TechniquesEngineering	2003	145
A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling Chih-Kong Ken Yang, R. Farjad-Rad, Mark Horowitz IEEE Journal of Solid-State Circuits Hardware SecuritySystem On ChipDigital Phase PickingVlsi DesignEngineering	1998	135
A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter R. Farjad-Rad, Chih-Kong Ken Yang, Mark Horowitz, IEEE Journal of Solid-State Circuits System On ChipEngineeringVlsi DesignEye OpeningMultiplexing	1999	112
A second-order semidigital clock recovery circuit based on injection locking Hiok-Tiaq Ng, R. Farjad-Rad, M.-J.E. Lee, IEEE Journal of Solid-State Circuits Electrical EngineeringInjection LockingEngineeringClock RecoveryData Converter	2003	64
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR Brian Leibowitz, Jade Kizer, Haechang Lee, Spectrally Gated AdaptationEngineeringEqualization UpdatesData ConverterMixed-signal Integrated Circuit	2007	53
A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver R. Farjad-Rad, Chih-Kong Ken Yang, Mark Horowitz, Signal IntegrityEngineeringMultiplexingTransmitted 8-Gbps DataClock Recovery	2003	49
0.622-8.0 Gbps 150 mW serial IO macrocell with fully flexible preemphasis and equalization R. Farjad-Rad, Hiok-Taiq Ng, M.-J. Edward Lee, Gbps TransceiverTransmitter MacrocellElectrical EngineeringEngineeringVlsi Design	2004	45
A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os R. Farjad-Rad, An Nguyen, James Tran, IEEE Journal of Solid-State Circuits System On ChipElectrical EngineeringEngineeringVlsi DesignClock Recovery	2004	40

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