IEEE Journal of Solid-State Circuits · 1992 · 282 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesAnalog IntegrationCmos Circuit DesignDynamic Power ReductionLookup TablesLow-power Digital Circuit DesignComparator DesignComparatorsFlip-flop DesignFlip-flopsHigh-speed Cmos DesignLatch DesignOffset CancellationPower Consumption
A comparator consisting of a differential input stage, two regenerative flip-flops, and an S-R latch is presented. No offset cancellation is exploited, which reduces the power consumption as well as the die area and increases the comparison speed. An experimental version of the comparator has been integrated in a standard double-poly double-metal 1.5- mu m n-well process with a die area of only 140*100 mu m/sup 2/. This circuit, operating under a +2.5/-2.5-V power supply, performs comparison to a precision of 8 b with a symmetrical input dynamic range of 2.5 V (therefore +or-0.5 LSB resolution is equal to +or-4.9 mV).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
5
An 8-bit high-speed CMOS A/D converter
Takuya Kumamoto, M. Nakaya, Hiroki Honda et al. · IEEE Journal of Solid-State Circuits · 1986 · 52 citations
Engineering, Computer Engineering, Electrical Engineering +17